Circuit of reducing transmission delay for synchronous DRAM
US6130848A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1997 |
| Grant date | Oct 10, 2000 |
| Priority date | — |
| Expiry date | Dec 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for reducing the transmission delay of the SDRAM by using a cascade-amplifying scheme. The circuit principally encompasses a memory array core for storing data, a main amplifier for initially amplifying the data, an MO-pair receiving amplifier for recognizing and amplifying the data, and an output neighborhood for outputting the data when the data convey a log data path. When the required data output from the memory array core is amplified by the main amplifier, the differential level of the required data will appear at both the far end and the near end of the data path. Therefore, the transmitted data at the far end can be amplified again as long as the differential level is sufficient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.