Planar cache layout and instruction stream therefor
US6131152A · kind A · utility
30Cited by
13References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 1996 |
| Grant date | Oct 10, 2000 |
| Priority date | — |
| Expiry date | May 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0895
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cache layout is simplified by swizzling the bits of instruction words. Then the words are read out of cache by using a shuffled bit stream which simplifies cache layout. The object is further met using a cache structure which includes a device for storing a shuffled instruction stream; and a device for multiplexing bits from the storage means onto the bus so that the bits are deshuffled. The multiplexing means includes a multiplicity of lines leading from the storage device to the bus. The read lines do not cross each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.