Method and apparatus for testing an integrated circuit
US6133054A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 2, 1999 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Aug 2, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2856
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and an associated article of manufacture in which a conductive layer is formed over an uppermost level of interconnect on a semiconductor substrate. The conductive layer is then patterned to form conductive members. At least one of the conductive members includes a first fuse structure in series with a first bond pad portion. The bond pad portion forms an electrical contact with a corresponding integrated circuit device. A voltage is then applied to the device via the conductive member and the bond pad portion. The fuse structure is adapted to form an open between the conductive member and the bond pad portion if the current in the fuse exceeds a predetermined threshold. After the voltage has been applied and the testing completed, the patterned conductive layer is then removed from the semiconductor device prior to final assembly or packaging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.