Method for forming an integrated circuit

US6133093A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Erwin J. Prinz · Austin, US
• Gregory Munson Yeric · Austin, US
• Kevin Yun-Kang Wu · Austin, US
• Wei-Ming Chen · Hsinchu, TW
• Frank K. Baker, Jr. · Austin, US

Key dates

• Filing date: Jan 30, 1998
• Grant date: Oct 17, 2000
• Expiry date: Jan 30, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/49

Abstract

In one embodiment, the reliability of an integrated circuit having a floating gate device (50), a high breakdown voltage transistor (52), and a low breakdown voltage transistor (54), which are electrically isolated from each other by a trench isolation region (12), is improved by using an oxidation resistant layer (24). The oxidation resistant layer (24) protects portions of the trench isolation region (12) when the gate dielectric layer (30) for the high breakdown voltage transistor (52) is formed, and when the gate dielectric layer (36) for the low breakdown voltage transistor (54) is formed. The oxidation resistant layer (24) minimizes etching of the field isolation region (12) so that thinning or recessing of the field isolation region (12) is minimized.