Silicon-on-insulator (SOI) hybrid transistor device structure

US6133591A · kind A · utility

Assignee

• Philips Electronics North America Corporation · US

Inventors

• Theodore Letavic · Putnam Valley, US
• Satyen Mukherjee · San Jose, US
• Arno Emmerik · Malden, NL
• J. Van Zwol · Waalre, NL

Key dates

• Filing date: Jul 24, 1998
• Grant date: Oct 17, 2000
• Expiry date: Jul 24, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/142

Abstract

A silicon-on-insulator (SOI) hybrid transistor device structure includes a substrate, a buried insulating layer on the substrate, and a hybrid transistor device structure formed in a semiconductor surface layer on the buried insulating layer. The hybrid transistor device structure may advantageously include at least one MOS transistor structure and at least one conductivity modulation transistor structure electrically connected in parallel. In a particularly advantageous configuration, the MOS transistor structure may be an LDMOS transistor structure and the conductivity modulation transistor structure may be an LIGB transistor structure, with the hybrid transistor device being formed in a closed geometry configuration. This closed geometry configuration may have both substantially curved segments and substantially straight segments, with MOS structures being formed in the curved segments and conductivity modulation transistor structures being formed in the straight segments. Hybrid transistor device structures in accordance with the invention feature excellent operating characteristics in high current, high voltage circuit applications, and in particular in source-follower circuit…