SOI-body selective link method and apparatus
US6133608A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1998 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Apr 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A silicon-on-insulator (SOI) structure and method of making the same includes an SOI wafer having a silicon layer of an original thickness dimension formed upon an isolation oxidation layer. At least two p-type bodies of at least two SOI field effect transistors (PFETs) are formed in the silicon layer. At least two n-type bodies of at least two SOI field effect transistors (NFETs) are also formed in the silicon layer. Lastly, an SOI body link is formed in the silicon layer of the SOI wafer adjacent the isolation oxidation layer for selectively connecting desired bodies of either the p-type SOI FETs or the n-type SOI FETs and for allowing the connected bodies to float.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.