High performance flip chip package
US6133634A · kind A · utility
188Cited by
33References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 5, 1998 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Aug 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
An improved semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. A silicon die is attached to a carrier (or substrate) that has a cavity substantially surrounding the die. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of the die as well as the edges of the carrier surrounding the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.