Tri-state input detection circuit
US6133753A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1998 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Nov 25, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A tri-state input detection circuit produces two binary outputs that indicate whether a tri-state input signal is high, low, or in a hi-impedance state. A pair of transistors conduct a current in response to a tri-state signal presented at an input node. Circuitry is provided to pull the input node to a known voltage when the input signal is in its hi-Z state. The transistors are series-connected to respective current sources, with the junctions between the transistors and their current sources forming the circuit's binary outputs. The output impedances of the current sources are made less than those of their respective transistors, so that when turned on by the input signal, a transistor pulls its associated output high or low. The circuit produces a unique binary output for each of the three input signal states. In a preferred embodiment, sampling pulses briefly activate the circuit, and downstream circuitry latches the circuit's outputs, reducing current consumption to zero except during the sampling period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.