Comparator circuit and method
US6133764A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1999 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Jan 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2472
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator circuit (10) with hysteresis having transistors with the same threshold voltage and a method for comparing input signals. The comparator circuit (10) includes a current mirror (11) coupled to a common electrode differential pair (12) and to a feedback circuit (13). The current mirror (11) has a large output impedance and provides a plurality of output currents (I.sub.21, I.sub.26, I.sub.31). Some (I.sub.21, I.sub.26) of the currents are transmitted to the common electrode differential pair and one (I.sub.31) of the currents is transmitted to the feedback circuit (13). The output currents (I.sub.21, I.sub.26, I.sub.31) are modulated to generate positive feedback signals that control changing the output state of the comparator circuit (10) as well as provide hysteresis for the comparator circuit (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.