GPS receiver having power management
US6133871A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 1996 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Mar 8, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2001/3894
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A GPS receiver having a low power mode of operation in one embodiment includes an antenna which receives GPS signals at an RF frequency from in view satellites; a downconverter coupled to the antenna for reducing the RF frequency of the received GPS signals to an intermediate frequency (IF); a digitizer coupled to the downconverter and sampling the IF GPS signals at a predetermined rate to produce sampled IF GPS signals; a memory coupled to the digitizer storing the sampled IF GPS signals; and a digital signal processor (DSP) coupled to the memory and operating under stored instructions thereby performing operations on the sampled IF GPS signals to provide pseudorange information. In one example, after the sampled IF GPS signals have been stored in the memory, the GPS receiver front end is powered down and the DSP is powered up. The GPS receiver in one embodiment also includes other power management features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.