Mask arrangement for scalable CAM/RAM structures
US6134135A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 10, 2000 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Jan 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a CAM/RAM memory device with a scalable and flexible structure. The device has a number of rows of memory cells. At least one address decoder is connected by word lines to the cells of the rows. Vertical bit lines for match data implement CAM functionality of the memory device. According to the invention a mask is implemented in a row of the memory cells, the mask affecting the match data on the bit lines. Preferably, the memory device is divided into segments with a mask at the top of each segment. By means of the present invention, masking is obtained by inserting masks as mask rows between the CAM rows. The mask rows are programmed by writing the mask row cells in the same way as the CAM cells. The mask rows operate directly on the bit lines for the whole underlying segment of rows. By means of this arrangement, the invention makes efficient use of the available silicon area. The memory device has a useful application as a device for handling address look-up, e.g. in a switch or router.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.