Semiconductor memory and redundant circuit
US6134159A · kind A · utility
2Cited by
3References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 24, 1999 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Aug 24, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory includes a memory array; data buses connected to the memory array; a plurality of data transmission circuits connected to the data buses one by one; and a buffer circuit connected to an outside device. The memory further includes a gate circuit arranged between the data transmission circuits and the buffer circuit; and a fuse connected to the gate circuit. The data transmission circuits are selectively connected to the buffer circuit by controlling the fuse and the gate circuit, so that a defective element is replaced with a normal element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.