Patent · US Expired

Programmable logic array integrated circuit incorporating a first-in first-out memory

US6134166A · kind A · utility

55Cited by

23References

20Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Craig Lytle · Mountain View, US
Donald F. Faria · San Jose, US

Key dates

Filing date	Feb 5, 1998
Grant date	Oct 17, 2000
Priority date	—
Expiry date	Feb 5, 2018

Classification

Technology area (CPC G)Physics
CPC primaryG06F5/10
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A programmable logic device integrated circuit incorporating a first-in, first-out memory block (250). First-in, first-out memory block (250) is coupled to a programmable interconnect array (213). Signals from the logic array blocks (LABs) (201) are connected to the control inputs of the first-in, first-out memory (250). In one embodiment, the programmable interconnect array (213) may be programmably coupled to the control inputs (259) of the first-in, first-out memory block. Status flag signals (276) from the first-in, first-out memory block (250) are programmably coupled to the programmable interconnect array (213). Data input (263) and data output (261) to first-in, first-out memory block (250) may be coupled to external, off-chip circuitry.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.