Method and apparatus for simulating large, hierarchical microelectronic resistor circuits
US6134513A · kind A · utility
17Cited by
10References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 23, 1997 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Oct 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented method for simulating a resistive circuit, including a plurality of macro circuits that are arranged hierarchically. The method includes the steps of reading a netlist description of the resistive circuit and recursively traversing the resistive circuit starting from terminal nodes of a macro circuit at a highest level of hierarchy using precharacterizations of each of the plurality of macro circuits to determine node voltages and branch currents of the resistive circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.