Method and system for taking advantage of a pre-stage of data between a host processor and a memory system
US6134623A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 1998 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Aug 21, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for coupling a host processor to a memory subsystem and enabling efficient transfer of data therebetween, where the memory subsystem responds to a data block read request by dispatching the designated data block and N data segments that are used by the receiver to determine the integrity of the data transfer. The system comprises a first bus system which couples the memory subsystem, via a bridge, to a controller that is, in turn, coupled by a second bus system to the host processor. The controller responds to a read request from the host processor for a first data block by dispatching to the bridge modified read requests that include (i) an address of the first data block and (ii) an address for the N data integrity segments. The bridge transfers the modified read requests to the memory subsystem, receives the first data block from the memory subsystem and transfers it to the controller. The bridge then receives the N data integrity segments, uses them to check the integrity of the data transfer, and discards them. Because of the aforesaid handling of the N data integrity segments, the bridge, upon receiving a next read request of data in addresses that are sequential to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.