Computing system having multiple nodes coupled in series in a closed loop
US6134647A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1999 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Apr 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/42
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a plurality of nodes, a serial data bus interconnecting the nodes in series in a closed loop for passing address and data information, and at least one processing node. In one construction, this processing node has a processor, a printed circuit board, a memory partitioned into first and second sections and a local bus connecting the processor, a block sharable memory section of the memory, and the printed circuit board. The local bus is used for transferring data in parallel from the processor to a directly sharable memory section of the memory on the printed circuit board and for transferring data from the block sharable memory to the printed circuit board. The printed circuit board includes a sensor for sensing when data is transferred into the directly sharable memory, a queuing device for queuing the sensed data, a serializer for serializing the queued data, a transmitter for transmitting the serialized data onto the serial data bus to the next successive processing node, a receiver for receiving serialized data from next preceding processing node, and a deserializer for deserializing the received serialized data into parallel data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.