Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same
US6136662A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 1999 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | May 13, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The method also includes the step of fabricating a number of alignment trenches in the first conductor layer. Moreover, the method includes the step of depositing a first insulator layer on the first conductor layer so as to fill the number of alignment trenches. Yet further, the method includes the step of removing material associated with the first insulator layer from the number of alignment trenches such that an upper surface of the first conductor layer and an upper surface of the first insulator layer define a first alignment step feature which possesses a predetermined height. The method also includes the step of depositing a second conductor layer on the semiconductor wafer subsequent to the removing step. A semiconductor wafer is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.