Reduction of parasitic through hole via capacitance in multilayer printed circuit boards
US6137061A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 1997 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Aug 1, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10189
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A printed circuit board that reduces parasitic effects on devices mounted thereon. The printed circuit board comprises a top layer and a bottom layer of a first insulating material having a first dielectric constant. The layers are configured to form holes whereby each of the holes has a first part extending through the top layer and a second part extending through the bottom layer. The bottom layer is further configured to comprise a second insulating material having a second dielectric constant, which second insulating material surrounds the second part of the hole. The devices mounted onto the printed circuit board have pins that extend through the holes. When the second dielectric constant is less than the first dielectric constant, the parasitic effects on the pins of the mounted devices are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.