Lead on chip semiconductor device and method of fabricating the same
US6137159A · kind A · utility
13Cited by
1References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1999 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Feb 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form a depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.