Interposer array module for capacitive decoupling and filtering
US6137161A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1999 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Sep 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a circuit chip which presents electrical contacts configured and aligned for attachment to corresponding contacts on a supporting substrate. The semiconductor package further includes an interposer with upper surface contacts aligned with the circuit chip contacts and lower surface contacts aligned with the corresponding contacts on the supporting substrate. The interposer includes a series of ground plane layers which are capacitively coupled to the conductors that connect the upper surface contacts to the lower surface contacts. The ground plane layers closest to the circuit chip have plates therebetween and electrically separated therefrom which are connected to the power input supply lines to form decoupling capacitances. The ground plane layers more remote from the circuit chip have, therebetween and electrically separated therefrom, conductive flange portions attached to individual signal lines to form a low pass feed through filter for each signal line. The capacitance of the flange portions is designed to establish the correct roll off to pass the desired signals and shunt to ground the unwanted harmonics while the decoupling capacitance is …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.