Field emission flat panel display with improved spacer architecture
US6137212A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 1998 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | May 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J31/127
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method for forming a field emission flat panel display includes deposit a conductive patterned layer on a substrate, depositing an emitter material over the patterned layer, patterning the emitter material to provide a series of mask caps, etching the emitter material to provide arrays of emitter peaks with the mask caps thereon, depositing a dielective layer on the patterned layer and on the mask caps, depositing a conductive gate layer on the dielectric layer, depositing a high-resistivity dielectric layer on the gate layer, depositing a low-resistivity dielectric layer on the high-resistivity dielectric layer, and etching away portions of the dielectric layer, gate layer, high-resistivity dielectric layer and low-resistivity dielectric layer to expose the mask caps, and removing the mask caps to expose the emitter peaks to provide an emitter cathode panel, providing a transparent panel having a conductive coating thereon, and depositing a layer of thin film phosphors on the conductive coating to provide an anode screen, and attaching the anode screen to the cathode panel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.