Method and apparatus for simultaneously performing a plurality of compare operations in content addressable memory device
US6137707A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1999 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Mar 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for simultaneously performing a plurality compare operations in a content addressable memory (CAM) device. For one embodiment, the CAM device includes a CAM array having a plurality of CAM cells, a first comparand register for storing first comparand data, and a second comparand register for storing second comparand data. Each CAM cell receives the first comparand data over a first set of compare lines, and receives the second comparand data over a second set of compare lines. Each CAM cell has a memory cell and multiple compare circuits that can individually and simultaneously compare the first and second comparand data with data stored in the memory cell. The result of each comparison is reflected on a corresponding match line. The match lines are then selectively coupled to a priority encoder to determine a match address corresponding to each compare operation. For one embodiment, the CAM cells may be ternary CAM cells each having a mask cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.