Row decoding circuit for a semiconductor non-volatile electrically programmable memory and corresponding method
US6137725A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 1998 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Dec 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of the type which includes a matrix of memory cells laid out as cell rows and columns and is divided into sectors, said circuit being input row decode signals and supply voltages in order to drive an output stage incorporating a complementary pair of high-voltage MOS transistors of the pull-up and pull-down type, respectively, which are connected to form an output terminal connected to the rows of one sector of the matrix, characterized in that a MOS transistor of the P-channel depletion type with enhanced gate oxide is provided between the output terminal and the pull-down transistor. The control terminal of the depletion transistor forms a further input of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.