Computer memory interface having a memory controller that automatically adjusts the timing of memory interface signals
US6137734A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1999 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Mar 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller features programmable delay buffers that allow the memory interface signals to be automatically adjusted. By fine tuning the delay values, the memory controller can compensate for impedance characteristics that affect the memory interface timing. The memory controller includes a built-in self test mode, in which it runs a series of memory tests using a plurality of different delay combinations for the delay buffers. After running the built-in self test, the memory controller programs the delay buffers to values which allow the memory transactions to occur without errors, ensuring optimal memory interface timing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.