Phase detector circuit and method of phase detecting
US6137852A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1997 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Dec 23, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An image reject receiver (10) uses a mixer circuit (12) and a mixer circuit (16) to frequency translate an incoming reference signal (RF.sub.IN) and generate a first output signal (V.sub.OUT1) and a second output signal (V.sub.OUT2), respectively. Two phase detectors (26 and 36) measure a phase difference between the first and second output signals (V.sub.OUT1, and V.sub.OUT2) and a difference circuit (30) provides a difference value in accordance with the phase difference. The difference value cancels any phase shift due to time delays associated with the phase detectors (26 and 36). The difference value is fed back to a phase shift circuit (20) for adjusting the phase of the second output signal (V.sub.OUT2) and locking the first output signal (V.sub.OUT1) in-phase with the second output signal (V.sub.OUT2).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.