Circuit and method of generating a phase locked loop signal having an offset reference
US6137995A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1998 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Dec 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated transceiver circuit (10) includes a single side-band mixer (12) and a phase locked loop (30). The phase locked loop (30) includes a phase detector (32) coupled to a voltage controlled oscillator (36) via a summing circuit (33) and a low pass filter (34). A feedback signal from the voltage controlled oscillator (36) is transferred to the phase detector (32) through a counter (38). Either a phase modulation signal or a frequency modulation signal are inputs of summing circuit (33) and modulate the transmitter carrier signal generated by the voltage controlled oscillator (36). The carrier signal generated at an output terminal (40) of the transmitter tracks the frequency of the local oscillator signal that is supplied at an input terminal of the single side-band mixer (12) in the receiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.