Microprocessor cache consistency
US6138216A · kind A · utility
7Cited by
5References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 21, 1998 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Jan 21, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0837
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is described of managing memory in a microprocessor system comprising two or more processors (40, 42). Each processor (40, 42) has a cache memory (44, 46) and the system has a system memory (48) divided into pages subdivided into blocks. The method is concerned with managing the system memory (48) identifying areas thereof as being "cacheable", "non-cacheable" or "free". Safeguards are provided to ensure that blocks of system memory (48) cannot be cached by two different processors (40, 42) simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.