Microprocessor with rate of instruction operation dependent upon interrupt source for power consumption control
US6138232A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1997 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Dec 19, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor operates at a rate dependent upon the interrupt source of a plurality of interrupt sources. The rate of power consumption by the microprocessor corresponds to the selected rate of instruction operation. A rate table accessed upon receipt of an interrupt stores a table of interrupt source to rate of instruction operation. The rate table may be a read only memory or a read/write memory loaded upon initiation of the microprocessor. The rate of microprocessor instruction operation may be set by frequency of an instruction clock or by a rate of instruction dispatch. For a superscalar microprocessor the rate of instruction operation may be set by setting a number of instructions dispatched per instruction cycle. On receiving an interrupt a rate number is pushed onto a rate stack. On return from the interrupt the rate stack is popped. The microprocessor operates at a rate corresponding to the rate number at a top of the rate stack. The invention may be coordinated with system management mode power control. A predetermined system management mode rate number is pushed onto the rate stack upon receipt of a system management interrupt entering the system management mode. The …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.