Method for switching between multiple system processors
US6138247A · kind A · utility
60Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 1998 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | May 14, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method for switching between multiple system processors (152,172) on a CompactPCI bus (110,120), when a standby system processor (172,152) determines a failure affecting an active system processor (152,172) on the CompactPCI bus (110,120), the standby system processor (172,152) places a special arbiter (820) in a one master mode. If the standby system processor (172,152) determines that a device is at risk of performing a destructive action, the standby system processor (172,152) quiesces the device. The standby system processor (172,152) then places the special arbiter (820) in a multiple master mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.