Circuits, architectures and methods for detecting and correcting excess oscillator frequencies
US6140880A · kind A · utility
12Cited by
17References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1998 |
| Grant date | Oct 31, 2000 |
| Priority date | — |
| Expiry date | Sep 24, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and method for preventing an oscillator from oscillating above a first predetermined frequency or below a second predetermined frequency. The present invention may comprise (a) a clock generation circuit configured to generate an output clock signal in response to (i) a reference clock, (ii) one or more control signals and (ii) a reset signal and (b) a control circuit configured to generate said reset signal in response to said one or more control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.