Clock generating circuits that utilize analog pump signals to provide fast synchronization and reduced delay skew
US6141292A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1999 |
| Grant date | Oct 31, 2000 |
| Priority date | — |
| Expiry date | Aug 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Clock generating circuits include a clock buffer, a delay mirror circuit (DMC), a clock frequency divider circuit and a clock generator circuit. The clock buffer is responsive to an external clock signal EXTCLK and generates a buffered clock signal ICLK in response to the external clock signal EXTCLK. The buffered clock signal ICLK is delayed relative to the external clock signal EXTCLK by a fixed buffer delay time "dtb". The delay mirror circuit (DMC) is responsive to the buffered clock signal ICLK and generates a delayed clock signal IDCLK. The delayed clock signal IDCLK is delayed relative to the buffered clock signal ICLK by a fixed delay-mirror time "dtot". The clock frequency divider circuit is responsive to the buffered clock signal ICLK and the delayed clock signal IDCLK. The clock frequency divider circuit includes first and second divider devices that generate first and second divided clock signals VDIV1 and VDIV2, respectively. The clock generator circuit is responsive to VDIV1 and VDIV2 and includes a control signal generator, an analog pump signal generator and a driver circuit. Based on this configuration of the above-described circuits, only 2 clock periods are requi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.