Method of asynchronous memory access
US6141721A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1999 |
| Grant date | Oct 31, 2000 |
| Priority date | — |
| Expiry date | Mar 18, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/91
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of asynchronously accessing a random access memory having a plurality of rows and columns, where each row has a wordline connected to read and write row decoders and each column is connected to bitlines. A row address is assigned to a first and second row, i.e. a pair of rows. A read address is provided to the read row decoder and a write address is provided to the write row decoder. The read and write addresses are decoded by the read and write row decoders, respectively, and one of the first or second rows is selected for reading. Asynchronous with selecting one of the first or second rows for reading, one of the first or second rows is selected for writing. Data is then read from the row selected for reading and asynchronously data is written into the row selected for writing. Signals are provided which coordinate the reading and writing of data, where in the event reading or writing is being performed, another of the reading or writing is deferred until completion of the first reading or writing. The read row decoder and the write decoder are unable to select the same row simultaneously and a read control circuit and a write control circuit are unable to select the sam…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.