Electronic chip package
US6143401A · kind A · utility
31Cited by
77References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 16, 1998 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Jan 16, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/3154
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic chip package is provided having a laminated substrate. The laminated substrate includes at least one conductive layer and at least one dielectric layer which is bonded to the conductive layer. The dielectric layer has a glass transition temperature T.sub.g greater than 200.degree. C. and a volumetric coefficient of thermal expansion of .ltoreq.75 ppm/.degree.C. A semiconductor device is electrically attached to the laminated substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.