Semiconductor substrate and method of manufacturing the same
US6143628A · kind A · utility
119Cited by
3References
82Claims
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Key dates
| Filing date | Mar 25, 1998 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Mar 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2007
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method excellent in controllability, productivity and economics of a high-quality SOI wafer and a wafer manufactured by that method are provided. After wafer bonding, separation is made on an interface of a high porosity layer in a porous region including a low porosity layer and the high porosity layer in a surface formed on a main surface side of a first Si substrate 2 to transfer a non-porous layer onto a second substrate. After separation at the high porosity layer, a residual low porosity thin layer is made non-porous by a smoothing process such as hydrogen annealing without using selective etching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.