Semiconductor device having impurity concentrations for preventing a parasitic channel
US6144047A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 27, 1998 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Jan 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76213
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is herein disclosed which comprises a plurality of element regions 50 formed on a first conductive type semiconductor substrate 60, element isolation regions 58 for isolating the element regions from each other, and gate electrodes 54 on parts of the element regions, the element regions being in contact with the element isolation regions at side surfaces 68 of the element regions, wherein in the element region under each gate electrode, the concentration of a first conductive type impurity is high in an element region top surface edge area (in the vicinity of 66), and on the side surfaces of each element region, except the portions under the gate electrode, the concentration of the first conductive type impurity is equal to or lower than that of the first conductive type impurity in the body of the element region. According to the present invention, in the semiconductor device having a trench isolation, the formation of a parasitic channel at element region top surface edges under a gate electrode can be prevented and a leak current in an OFF state can be reduced without any increase in a junction capacitance which retards the driving velocity of elements and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.