Method and apparatus for use in IDDQ integrated circuit testing
US6144214A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 1998 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Oct 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3012
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A built in current sensor circuit (BICS) for use in integrated circuit testing utilizing the Quiescent Power Supply testing technique comprised of a detecting transistor, an s-ram cell and a buffer cell electrically coupled in a cascaded configuration to perform a comparator function, a reference source comprised of a current generating transistor and a voltage level setting transistor, and an active output load comprised of a single p-MOSFET sized to draw a unique amount of current when a respective circuit under test is determined to be defective., whereby the additional current drawn by the active output load is readily observable on the bias line by an external standard off-the-shelf current monitor. The built in current sensor circuit thereby alleviates the excessive use of area overhead in deep submicron integrated circuits and the need for separately propagating a defect signal to an output pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.