Low switching noise logic circuit
US6144217A · kind A · utility
13Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1999 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Jul 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-digital hybrid IC device for reducing cross-talk adds an electrostatic capacitance element to the power supply side and/or the ground side of a CMOS logic circuit forming the digital circuit part, connects a resistance between the electrostatic capacitance element and the terminal to which the electrostatic capacitance element was added, and buffers charging and discharging when the logic elements switch on and off to reduce noise produced by current peaks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.