Generalized push-pull cascode logic technique
US6144228A · kind A · utility
2Cited by
3References
42Claims
0Family size
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Key dates
| Filing date | Jun 28, 1999 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5352
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are presented for efficient implementation of logic and arithmetic functions that generate sets of mutually exclusive output signals. Such a logic family includes a network of NMOS transistors that implements a desired logic function. Coupled to that network is a minimal number of PMOS devices for providing logic level restoration and for compensating for any voltage drops due to the NMOS transistors. With such a structure, the speed, area and power consumption characteristics of logic functions are improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.