Analog to digital converter with a differential output resistor-digital-to-analog-converter for improved noise reduction
US6144331A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 8, 1998 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Apr 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved successive-approximation type ADC that uses both charge-scaled and voltage scaled approximation. The present invention provides a high noise immunity, high speed ADC using a differential voltage scaled DAC. The differential voltage scaled output scheme of the present invention advantageously applies voltage scaling to a capacitor on both inputs to the comparator. The dual voltage scaling is preferably done by connecting two switches to each tap on the bottom half of a resistor string, and no switches to the top half of the resistor string, using one set of tap switches for adjusting a charge on capacitor on the first input of the comparator and the second set of tap switches for adjusting a charge on capacitor on the second input of the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.