Interprocessor communication circuitry and methods
US6145007A · kind A · utility
39Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1997 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Nov 14, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of exchanging messages between first and second processors. A pending flag in a first register is polled by the first processor and if the flag is in a first selected logic state, a message is written into a second register with the first processor. The pending flag is set to a second selected logic state with the first processor and an interrupt to the second processor is generated. The message is read from the second register with the second processor when the pending flag is in the second logic state. The pending flag set to the first logic state with the second processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.