System for managing input/output address accesses at a bridge/memory controller
US6145030A · kind A · utility
15Cited by
15References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 27, 1998 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Mar 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0866
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.