Management of display FIFO requests for DRAM access wherein low priority requests are initiated when FIFO level is below/equal to high threshold value
US6145033A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 17, 1998 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Jul 17, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A display FIFO module is used in a DRAM interface. A low priority request and high priority request are both issued when the FIFO must receive new data or FIFO underrun will occur. This is determined by comparing the FIFO data level against a predetermined high threshold value. After a predetermined number of addresses have been latched by a DRAM controller sequencer to the DRAM for transferring data to the FIFO because of either the low or high priority request, or both, the display FIFO module reevaluates the FIFO data level to determine whether the FIFO data level is still below or is equal to either the low or high threshold value. If the FIFO data level is still below or equal to the low threshold value, the low priority request remains active; otherwise, the low priority request will be removed by the display FIFO module. Similarly, if the FIFO data level is still below or equal to the high threshold value, the high priority request remains active; otherwise, the high priority request will be removed by the display FIFO module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.