Timing protocol for a data storage system
US6145042A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 23, 1997 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Dec 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0866
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes a bus having: an bus-select/address/command portion; bus-grant/data/clock-pulse portion; a bus queue portion; and an ending-status portion. A plurality of addressable memories is coupled to the bus. A plurality of controllers is coupled to the bus. Each one thereof being adapted: to assert on the bus-select/command/address portion of the bus, during a controller initiated bus select assert interval, a command. The addressed memory is adapted to produce on the queue portion of the bus a queue signal a predetermined time after a controller initiated bus select assert interval. The queue signal terminates the bus select interval. Another one of the controllers is adapted to provide on the bus-select/address/command portion of the bus another address and command after the queue signal terminates the bus select assert interval. The memory is adapted to write, in response to the write operation request by the controller during the bus grant interval, the data on the bus-grant/data/clock-pulse portion …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.