PCI bus bridge with transaction forwarding controller for avoiding data transfer errors
US6145044A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1998 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Sep 28, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus bridge which can prevent invalid data from being transferred from a secondary PCI bus to a primary PCI bus even when an SCSI controller or another device provided with a memory the content of which is cleared after a read, is connected to the secondary PCI bus. In a controller, a transaction is processed as a delayed transaction. A combination circuit generates a switching logic signal in accordance with a command or an address included in the transaction. In accordance with the memory content, a bus release controller restricts transmission by a transaction forward controller of a control signal for stopping the transaction issued on the primary PCI bus. Instead of restricting the transmission of the control signal, the time-out period of the buffer memory may be prolonged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.