Method for digital signal processing, DSP, mobile communication and audio-device
US6145070A · kind A · utility
0Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 15, 1997 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Aug 15, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/345
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a digital signal processor in which two multiply accumulate operations are carried out in one machine cycle. Only one address generation unit is required for addressing two data words of both the X and Y memories, since in the main processing loop the least significant address bit is considered as "Don't care", so that an access operation to the memory results in two output data words at a time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.