Metal-polycrystalline silicon-N-well multiple layered capacitor

US6146939A · kind A · utility

Assignee

• Tritech Microelectronics, Ltd · SG

Inventor

• Uday Dasgupta · Singapore, SG

Key dates

• Filing date: Sep 18, 1998
• Grant date: Nov 14, 2000
• Expiry date: Sep 18, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/212

Abstract

A stacked capacitor that has a large capacitance per unit area (Co), very low voltage coefficient (Kv), and an acceptable parasitic capacitance factor (Kp) is described that uses only one polysilicon layer. The stacked capacitor is formed at the surface of a semiconductor substrate of a first conductivity type. The stacked capacitor has a bottom plate that is formed by a lightly doped well diffused into the surface of the semiconductor substrate. The bottom plate also has a first plurality of interconnected conductive layers of a first conductive material disposed above and aligned with the well, whereby a first conductive layer of the first plurality of conductive layers is connected to the well by multiple contacts distributed over an area of the well. The stacked capacitor further has a top plate with a second conductive layer of a second conductive material such as a highly doped polycrystalline silicon placed between the well and the first conductive layer and has openings distributed over a surface area of the conductive material to allow the multiple contacts to connect the well and the first conductive layer. The top plate further has second plurality of interconnected cond…