Power consumption control mechanism and method therefor
US6147508A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 1998 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Aug 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for controlling the power consumption of a logic device are implemented. The power dissipation, and consequently, the speed of a complementary metal oxide semiconductor (CMOS) logic device is substantially proportional to the speed of the device. The temperature of the logic device is controlled by controlling the device speed by adjusting the threshold voltage of the metal oxide semiconductor (MOS) devices forming the logic device under control. The threshold voltage of the devices is controlled by applying a back bias voltage between the bulk material in which each device under control is fabricated, and the most positive electrode of the device. The back bias voltage value is regulated in response to the logic device temperature, thereby closing a feedback loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.