Integrated circuit for handling buffer contention and method thereof
US6147510A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 13, 1998 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Jul 13, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T83/2037
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an integrated circuit (10, 110) has a contention detection circuit (12, 112) coupled to a tri-stateable output buffer (18, 118). The contention detection circuit (12, 112) provides a contention tri-state control signal (34, 134) to the tri-stateable output buffer (18, 118) in order to place it in a tri-stated condition when an external device (31, 131), such as a computer, supplies power to an input/output pad (22, 122) on the integrated circuit (10, 110). Thus, external and/or internal buffer contention is avoided when an external device (31, 131), such as a computer, supplies power to an input/output pad (22, 122) on the integrated circuit (10, 110).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.