Method of invoking a power-down mode on an integrated circuit by monitoring a normally changing input signal
US6147528A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1998 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Mar 13, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprises means responsive to a normally changing signal at an input of the integrated circuit to implement a primary function of the circuit, and means for monitoring this normally changing signal at the input in question of the integrated circuit. This monitoring means is responsive to suspension of the normally changing signal to communicate a signal for implementation of a secondary function of the circuit. In an exemplary embodiment, the invention is directed towards implementation of power-down of the circuit, without using an explicit power-down or reset pin. An input signal which normally changes at minimum rate, e.g. preferably a clock signal, is held in a fixed state for a minimum duration to invoke the reset or power-down mode. An integrated circuit may thus be powered-down or reset where no explicit power-down or reset pin is available.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.