FPGA with embedded content-addressable memory
US6147890A · kind A · utility
71Cited by
22References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1998 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Oct 5, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Content Addressable Memory (CAM) core is integrated and interfaced with a configurable logic core (e.g., FPGA) on a single integrated circuit (IC) chip to permit a user to change algorithms for and to tailor word length to a particular application. Significant improvements in fetch times and overhead are achieved. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.